The advent of 5G and high-speed fibre-optic data networking has generated a requirement for faster clock oscillators running at ever higher frequencies.
Although the Covid-19 crisis has affected day to day business, oscillator manufacturers have continued to push the boundaries of oscillator design to achieve these higher clock speeds.
There are many challenges for the oscillator designer, but one of the main issues is how to generate higher frequencies while keeping both phase noise and phase jitter low.
The performance of standard CMOS clock oscillators degrades above 50MHz when the waveform starts to deteriorate from a square wave to a distorted shape depending on the loading of the output. As clock frequencies rise, gate transition times are too slow for fast propagation with current consumption tending to increase proportionately as a result while phase noise performance declines.
To achieve higher speed solutions, differential output devices such as Low Voltage Differential Signalling (LVDS) and Low Voltage Positive Emitter Coupled Logic (LVPECL) have been developed but these each have their own issues. Figure 1 below shows the difference between a CMOS output and the various types of differential output.
A comparison of the basic LVDS signalling levels with those of PECL shows that LVDS output devices exhibit half the voltage swing compared to that of PECL types and these are approximately one tenth of that of the traditional CMOS levels. Both LVDS and PECL oscillators also have limitations when it comes to phase noise and jitter in high-speed circuits.
The latest designs are moving towards newer techniques such as High-speed Current Steering Logic (HCSL) and Current Mode Logic (CML) outputs, which offer additional benefits and advantages over previous output formats.
The processing of increased amounts of data requires systems to run at much faster transfer speeds and this requires higher frequencies and faster transition times for oscillators. HCSL offers a constant current characteristic delivering a less “noisy” solution compared with static logic devices. This technology offers a high impedance output with fast switching times and, by fitting a 10 to 30Ω series resistor, any overshoot or ringing is reduced. This is a major benefit for mixed, low voltage signal processing, such as can be seen in optical networking.
The current consumption of HCSL generally lies between LVDS and PECL formats but offers faster speeds.This type of steering logic offers a constant current output; with a 15mA current source the current is “steered” between the true and complimentary outputs. Current steering techniques have also been used in bipolar technology with the sole objective of speeding up logic gates. It should also be noted that HCSL outputs require 50Ω termination as shown below in figure 2.
The latest Euroquartz oscillators offer frequencies up to 250MHz with enhanced jitter and phase noise performance as can be seen in figure 3.
As developments in 5G applications continue and demand for faster data transmission increases, so oscillator performance characteristics will be further enhanced. There is little doubt that the latest HCSL oscillator designs are set to become one of the key building blocks of networking technology for the future.Euroquartz is an independent UK-based manufacturer and supplier of quartz crystals, oscillators, filters and frequency-related products to the electronics manufacturing industry worldwide. The company is AS9100 registered and designs and manufactures a comprehensive range of frequency control components for a wide range of customers including major OEMs covering a broad spectrum of applications including defence and aerospace, communications, general electronics, computing, control systems and petrochemical among many others.